With the ever-increasing compute and memory bandwidth demands on data center servers, system implementers continuously strive to find novel techniques to provide higher performance for a wide range of application workloads while maintaining or even decreasing the cost of new infrastructure. The fundamental challenge of traditional servers results from being locked to specific memory types and having limited DRAM memory channels that prevent the flexibility needed to implement these techniques and optimize cost and performance metrics. Let’s look at how Compute Express Link’s CXL.memory sub-protocol can be used to create CXL™ memory controllers to:
● Expand memory bandwidth and/or capacity beyond what the host processor’s native DDR memory channels allow
● Enable host processors to have media-independence and support different memory types
● Decrease solutions costs by right-sizing memory capacity for targeted application workloads
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